Semiconductor devices are made in foundries, of which there are over a hundred worldwide (operated by approximately two dozen or so semiconductor companies adopting a foundry model). Fabrication of large-scale integrated semiconductor devices requires multiple process steps and mask layers that define etching and deposition patterns (e.g., for photoresists), dopant implants, and metallization. A semiconductor foundry may employ a particular set of process steps and mask layers for a given semiconductor device, and process steps/mask layers can differ significantly for different types of semiconductor devices (as well as similar devices made by different foundries). A particular set of process steps and mask layers employed by a given foundry to fabricate any of a variety of semiconductor devices is generally referred to as a “semiconductor manufacturing process technology” (or simply “semiconductor technology”). For fabrication of Complimentary-Metal-Oxide-Semiconductor (CMOS) devices, different manufacturing process technologies are sometimes commonly referred to as “CMOS technology nodes.” Some common examples of conventional CMOS technology nodes include a 45 nanometer silicon-on-insulator (SOI) process technology available from IBM (i.e., the IBM SOI12SO 45 nm technology), as well as the IBM SOI12SO 32 nm technology and the IBM 10LPE technology.
For each different semiconductor technology, a set of “design rules” is provided that includes a series of parameters specifying certain geometric and connectivity restrictions in connection with the manufactured semiconductor devices using a particular technology. Such design rules are based on the available process steps and mask layers in the given semiconductor technology, and provide sufficient margins to account for variability in the process steps used in the technology. Thus, design rules define allowed semiconductor design patterns to be converted to mask designs for the physical layout of a device in a given semiconductor technology. The specification of such technology-dependent design rules ensures reasonably predictable and sufficiently high yields for semiconductor device manufacturing using the given semiconductor technology (e.g., billions to trillions of nanoscale components can be fabricated simultaneously with high yield and performance).
Some examples of common design rules employed in a variety of conventional semiconductor technologies include “single layer rules” that specify geometric and connectivity restrictions on a given layer of a multi-layer semiconductor design. Examples of single layer rules include a “minimum size rule” that defines one or more minimum dimensions of any feature or object in a given layer of the design (e.g., a “width rule” that specifies the minimum width, in a plane parallel to the semiconductor substrate, of a feature or object in the design), and a “minimum spacing rule” that specifies a minimum distance between two adjacent features/objects in a given layer. Other examples of single layer rules relate to polygon-shaped elements, and include minimum/maximum area and allowed orientations of polygon edges. Other types of conventional design rules include “two layer rules” (specifying certain relationships that must exist between two layers, such as distance, extension or overlap between two or more layers). Design rule sets have become increasingly more complex with successive generations of semiconductor technologies.
Semiconductor devices conventionally are designed initially using “electronic design automation (EDA) tools,” which are a category of GUI-oriented software-based tools that support a design flow for facilitating the complete design and preliminary analysis of an entire semiconductor chip. Given the computer-aided-design functionality of EDA tools, they are also sometimes referred to as “electronic computer-aided design” (ECAD). These tools often rely on a “process design kit” (PDK) comprising a comprehensive library of parameterized “cells” that implement certain logic or other electronic functions. This facilitates a modular approach to design of electronic devices based on intuitive and standardized descriptions of various device elements and functions that may be compiled into invocations of cells. Libraries of such cells generally are provided for a given semiconductor technology together with a full description of electrical characteristics, physical dimensions and schematic representations all contained in the PDK, as well as simulation models. Examples of providers of EDA tools with well-developed and sophisticated PDKs for design of electronic devices include Synopsis, Cadence (which for example provides the “Virtuoso” EDA tool written in the SKILL language), Mentor Graphics, and Zuken.
By virtue of an EDA, electronic designers do not need to layout from scratch novel transistors or parameterized cells when creating designs for electronic devices to be fabricated in common CMOS semiconductor technologies. Rather, they may draw from an extensive library of parameterized cells in the PDK of the EDA to create designs for a large variety of integrated electronic devices. Moreover, these designs are automatically analyzed to ensure that, in the process of converting the designer's work into mask layers for the design of masks that will be used to manufacture the electronic device(s), no design rules are violated for the semiconductor technology being used—that is, the electronic designer's work is automatically analyzed and “cleaned” to ensure there are no violations of design rules associated with the semiconductor technology (i.e., there are no design rule check (DRC) violations).